The development of the semiconductor industry has always followed that of the Dynamic Random Access Memory (DRAM) technology in that the DRAM development has led to the use of the highest density technology elements capable of being produced in manufacturable quantities. The development of DRAM's in the 4 Megabit (4 Mb) density range began to depart from the twenty year tradition of two-dimensional DRAM designs by the appearance of three-dimensional DRAM cell structures, most notably by the use of trench capacitors. Proposed designs for DRAM cells in the 16 Mb, 64 Mb and higher density range have also included the use of multi-plate or stacked storage capacitor cell designs, see for example the article "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs," by T. Ema et al., International Electron Device Meeting (IEDM), Dec. 11-14, 1988, pp. 592-5, for a description of stacked DRAM cells.
Although the use of stacked cell technology has rendered the processing of DRAMs more complex, such techniques continue to be used extensively, as suggested by the article "A Novel Stacked Capacitor Cell with Dual Plate for 64 Mb DRAMs," by H. Arima et al., 1990 IEDM, paper 27.2, Dec. 9-12, 1990, pp. 651-4.
Although the preceding designers of DRAMs had taken satisfaction in designing DRAMs using the available microlithographic ground rules available to them, designers of 64 Mb DRAMs realized that they would be required to go far beyond the minimum ground rules of about 0.4 micron in order to provide capacitors of sufficient area to meet the requirements of 64 Mb DRAMs. As a result, there have been described several techniques for providing structures including sub-lithographic elements in order to enhance the surface area and, thus, the capacitance of DRAM capacitors by texturing or roughening the surface of polysilicon electrodes used as capacitor plates. For example, M. Sakao et al. describe in their paper at the 1990 IEDM, paper 27.3, pp. 655-8, how deposition of polysilicon at about 550 degrees C. yields hemispherical-shaped grains of polysilicon about 80 nm in diameter. Thus, surface irregularities in the order of about one-fifth that of the minimum lithographically definable feature are formed providing a potential doubling in capacitance per unit area in the plane of the substrate. These surface irregularities can be transferred to the surface of an underlying polysilicon layer by Reaction Ion Etching (RIE). Others, including M. Yoshimaru et al. in their 1990 IEDM paper 27.4, December 9-12, pp. 659-662, have shown that cylindrical polysilicon grains can be deposited having greater influence on the capacitance per unit surface area.
Surface roughness can be achieved by several methods. For example, partially oxidizing p+ polysilicon conductors leads to enhanced grain size as described in any of the following references: U.S. Pat. No. 4,119,995 to Simko on Oct. 10, 1978 describes a polysilicon roughening method in which wet oxidation and subsequent removal of oxide is used to promote the electrical discharge of a floating gate in a nonvolatile memory device. U.S. Pat. No. 4,314,265 to Simko describes the grain sizes in the range of about 450 Angstroms in width by about 750 Angstroms in height. This surface irregularity is substantially similar to the grain size described by Sakao et al. above. The article by P. C. Fazen et al. describes the preferable use of a silicon nitride layer adjacent to roughened polysilicon for capacitors requiring low leakage.
In addition, the roughening of the surface of polysilicon by the use of an anodic process has also been reported by Sandhu in U.S. Pat. No. 5,068,199 issued Nov. 26, 1991.
Porous silicon can be formed in monocrystalline silicon substrates to provide surface connected pores several times deeper than those of roughened silicon through the use of anodization in the presence of hydrofluoric acid. (See the articles "Microstructure and formation mechanism of porous silicon," by M. I. J. Beale, et al., Applied Physics letters, Jan. 1, 1985, pp. 86-88, and "Selective porous silicon formation in buried P+ layers," by S. S. Tasco, et al., J. Applied Physics 62(10), Nov. 15, 1987.) The porous silicon produced by this anodic process is somewhat similar to the process described above by Simko in that the oxidation process is enhanced along the polycrystalline grain boundaries.
Yet another method has been proposed to provide enhanced surface roughness by T. Mine et al. in the article "Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs," 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp. 137-140. Here, particles of photo-resist generated from an unidentified source are suspended in a spin on glass (SOG) film. The SOG is etched selective to the photoresist in order to leave resist particles on the surface of a polysilicon layer. After removal of the SOG, the underlying polysilicon is etched in the presence of the resist particles. While such a technique has potential for eclipsing those using surface roughening alone, it suffers from lack of a manufacturable method. In addition, because particulate sedimentation is relied on, insufficient randomness in distribution of the particles can occur.
While the prior art techniques have addressed the problem of increased capacitance, only minor success has been achieved. The subject invention is directed toward methods for significantly increasing the surface area and the effective capacitance of a given storage plate configuration.